In thin-film transistor liquid crystal display devices (hereinafter referred to as "TFT-LCDs"), there has been a trend in recent years toward large-screen, high-definition devices. Further, in accompaniment with the development of multimedia, increasingly high display quality is required of such liquid crystal display devices.
FIG. 12 is an explanatory drawing showing a panel 100 structured as conventional TFT-LCD panels are generally structured. In the panel 100, a glass substrate 131 is provided with scanning lines 101, signal lines 105, and TFTs 104, and an electrode is provided across the entire surface of another glass substrate 132. On the lower substrate in FIG. 12, i.e., the glass substrate 131, the lines extending laterally are the scanning lines 101, and those extending longitudinally are the signal lines 105. The lines 101 and 105 intersect with one another, but are separated from each other by a very thin insulating layer. Each intersection creates a small capacitance, and due to the very large number of scanning lines 101 and signal lines 105, the total of these capacitances for the entire panel 100 is a value which cannot be ignored.
Signal delay due to these capacitances in the lines is especially serious in large-screen, high-definition devices, and there may not be enough time to charge the pixels sufficiently.
Further causes of reduced panel productivity are short circuits due to insufficient insulation between the lines 101 and 105 where they intersect, line breakage where the level of a line changes, etc.
In order to resolve the foregoing problems, the following documents, for example, propose a panel structure in which TFTs and scanning lines are provided on one glass substrate, and signal lines on the other glass substrate.
(1) J. F. Clerc, et al, "New Electrode Architectures for Liquid Crystal Displays Based on Thin Film Transistors," Japan Display '86. PA0 (2) Kenichi OKI, et al, "Full Color Liquid Crystal Display Using a New Active Matrix," ITEJ Technical Report, Vol. 11,No. 27, pp. 73-78. PA0 (3) Kenichi OKI et al, "Active Matrix Display Device" (Japanese Unexamined Patent Publication No. 62-133478/1987 (Tokukaisho 62-133478, published on Jun. 16, 1987)).
FIG. 10 is an explanatory drawing showing a panel 30 structured according to the foregoing documents. In the present Specification, this type of structure will be referred to as the "counter substrate signal line structure."
In the panel 30 of the counter substrate signal line structure, a TFT substrate 31 is provided with scanning lines 1, reference potential lines 2, and TFTs 4; and a counter substrate 32 is provided with counter substrate signal lines 5. Accordingly, in the present structure, the scanning lines 1 and the counter substrate signal lines 5 do not intersect on opposite sides of an insulating thin film. This greatly reduces the capacitances created by intersections if the scanning lines 1 and the counter substrate signal lines 5, and signal delay based on the time constant of the lines is greatly reduced. For this reason, the counter substrate signal line structure is more suited to large-screen, high-definition TFT-LCDs, for which signal delay is a serious problem. Further, since the lines do not intersect on a single substrate, the likelihood of the foregoing short circuits and line breakage is reduced, which can be expected to improve production efficiency.
However, in the foregoing TFT-LCDs, when TFTs of non-monocrystalline silicon are used for the switching elements, crosstalk is marked, and it is difficult to suppress shift of the direct-current component. These problems are more serious in TFT-LCDs having a counter substrate signal line structure than in those having line intersections, because they appear as more marked phenomena.
The following will explain crosstalk in detail.
First, FIG. 13 shows an equivalent circuit diagram corresponding to a single pixel in the panel 100 having line intersections, and FIG. 11 shows an equivalent circuit diagram corresponding to a single pixel in the panel 30 of the counter substrate signal line structure.
In FIGS. 11 and 13, C.sub.LC is a capacitance due to the pixel electrode (hereinafter referred to as "pixel capacitance"); C.sub.gd is a capacitance between the gate and drain of the TFT 4 or 104 (including a coupling capacitance between the signal line and the pixel electrode); and C.sub.sd is a capacitance between the source and drain of the TFT 4 or 104 (including a coupling capacitance between the line to which the source electrode S of the TFT 4 or 104 is connected and the pixel electrode). Here, the line to which the source electrode S of the TFT 4 or 104 is connected is a signal line 105 in the panel 100 having line intersections, or a reference potential line 2 in the panel 30 of the counter substrate signal line structure.
Here, since a voltage applied to the liquid crystal is determined by a charge Q.sub.LC (not shown) of the pixel electrode when the TFT 4 or 104 is OFF, it is preferable, when the TFT 4 or 104 is OFF, to maintain the charge Q.sub.LC as uniformly as possible.
In the panel 100 having line intersections, shown in FIG. 13, factors causing fluctuation of the charge Q.sub.LC of the pixel electrode during the OFF state are relative potentials of the scanning lines 101 and the signal lines 105 with respect to a common electrode potential (V.sub.com). Of these, a potential difference between the common electrode potential (V.sub.com) and the scanning line potential (V.sub.g) can be held constant for all pixels. However, since signal line potential (V.sub.d) is a potential which varies depending on the pattern to be displayed on the panel 100, it cannot be held constant for all pixels.
In the same way, in the panel 30 of the counter substrate signal line structure, shown in FIG. 11, factors causing fluctuation of a charge Q.sub.LC (not shown) of the pixel electrode during the OFF state are relative potentials of the scanning lines 1 and the reference potential lines 2 with respect to a potential (V.sub.d) of the counter substrate signal lines 5. However, since the signal line potential (V.sub.d) of the counter substrate signal lines 5 is a potential which changes depending on the display pattern, neither of the foregoing can be held constant.
Since the scanning line potential (hereinafter referred to as "gate line potential") V.sub.g and the reference potential line potential (V.sub.ref) of each row are connected together at the corresponding TFTs 4, these cannot be changed in keeping with the signal line voltages (V.sub.d) of each pixel.
Accordingly, in the panel 30 of the counter substrate signal line structure, neither of the relative voltages of the gate line potential (V.sub.g) and the reference potential line potential (V.sub.ref) with respect to the signal line voltage (V.sub.d) can be held constant. If values of the pixel capacitance C.sub.LC, the capacitance C.sub.gd between the gate and drain of the TFT 4, and the capacitance C.sub.sd between the source and drain of the TFT 4 are assumed to be equal, then the panel 30 of the counter substrate signal l--line structure can be said to have the following structurally inherent problem: "the extent to which fluctuation of pixel electrode potential is dependent on the pattern to be displayed on the panel is essentially greater than in the panel 100 having line intersections."
In the panel 100 having line intersections, as will be discussed below, it is structurally easy to form supplemental capacitances in order to relatively reduce fluctuation of the potential of the pixel electrode, and this also indicates that it is easier to obtain high display quality with this structure than with the panel 30 of the counter substrate signal line structure. Further, fluctuation of the potential of the pixel electrode is observed as, specifically, smear arising depending on the display pattern, i.e., staining and unevenness (crosstalk or shadowing). Here, "crosstalk" means a phenomenon in a matrix display in which the display of a given domain influences the display of other domains in the same column or row through a bypass, thus driving other display pixels. Further, "vshadowing" is a synonym for "crosstalk."
The following will explain why it is difficult to suppress shift of direct-current components.
Generally, at the conclusion of writing to a pixel, the signal of the scanning line changes from select to non-select, and the voltage thereof is applied to the pixel capacitance C.sub.LC via a parasitic capacitance C.sub.par of the TFT. As a result, immediately after writing, potential of the pixel is always subject to a negative shift of a quantity proportional to C.sub.par /(C.sub.LC +C.sub.par) Normally, this negative shift can be compensated by adjusting the voltage which is used as a reference. However, since the dielectric constant of the liquid crystal changes depending on the effective voltage, the quantity of negative shift also changes, and it is not possible to compensate uniformly in-plane. With regard to display quality, this appears as a flicker component. Further, if the remaining direct-current component is large, staining and unevenness are likely to occur.
Consequently, in the panel 100 having line intersections, a supplemental capacitance C.sub.s is applied to reduce the dependence of the quantity of negative shift on the fluctuation in liquid crystal dielectric constant.
However, in the panel 30 of the counter substrate signal line structure, it is structurally very difficult to form a supplemental capacitance C.sub.s, and it is difficult to suppress flicker.